The present invention relates to a digital phase locked loop, and, more particularly, to a method for reducing switching noise in a digital phase locked loop.
Recent years have seen advancements in the field of electronic circuits and communication systems. Phase locked loops (PLLs) are an integral part of these systems. A PLL is used to generate an oscillating signal based on a reference signal. In communication systems, the oscillating signal is used for modulation and demodulation of a message signal and in electronic circuits the oscillating signal is used as a clock signal for synchronous operation of the circuit. Conventional PLLs were analog in nature and had various limitations such as bulky size due to their capacitor and resistor circuits. In newer technologies, the oxide thickness of the underlying semiconductor has been decreasing, and this has been problematic for a large area capacitor based analog loop filter because the gate leakage increases exponentially with oxide thickness reduction, and non-negligible gate leakage causes a large reference spur, which increases jitter in the output clock.
To overcome the above-stated limitations, a digital phase locked loop (DPLL) has been developed. FIG. 1 shows an example of a conventional DPLL 100. The DPLL 100 includes a phase-frequency detector (PFD) 102, a time to digital converter (TDC) 104, a digital filter 106, a digital to analog converter (DAC) 108, a current controlled oscillator (CCO) 110 and a divider 112.
The PFD 102 receives a reference signal generated by an external source and a feedback signal. The PFD 102 and compares the phase and frequency of these signals to generate an error signal whose magnitude depends on the phase and frequency difference between the reference signal and the feedback signal. The error signal is converted to a digital signal by the TDC 104. The digital error signal is transmitted to the digital filter 106, which attenuates high frequency noise components in the error signal and generates a control word signal based on the error signal. The control word from the digital filter 106 is transmitted to the DAC 108, which converts the control word to an analog control signal. The DAC 108 has one or more binary weighted current sources (not shown). The DAC 108 switches these current sources to a conducting state or a non-conducting state based on the control word to generate a current signal. The current signal is transmitted to the CCO 110, which generates the output signal based on the current signal. The output signal is transmitted to the divider 112, which reduces the frequency of the output signal by a predefined factor to generate the feedback signal.
The control word generated by the digital filter 106 switches the current sources of the DAC 108. For example, when the output signal has achieved a frequency/phase lock, which is a condition in which the frequency and phase of the reference signal are equal to the frequency and phase of the feedback signal, the value of the control word may be ‘01111’, which will cause four of the DAC current sources to a conducting state. If, in order to maintain the frequency/phase lock the control word has to be increased by 1 (e.g., incremented), the control word will change to ‘10000’, then four of the DAC current sources will switch to a non-conducting state and one current source will switch to a conducting state. Since the current sources are binary weighted, the instantaneous change in the magnitude of the current signal, due to the switching of the current sources, is large, which leads to generation of a current surge. This current surge is transmitted to the CCO 110, which results in high frequency jitter in the output signal. It would be advantageous to have a DPLL with reduced switching noise caused by current surges generated by switching of the DAC current sources.